Address Descramble

The internal circuitry in the OpticRAM scrambles the Row and Column Address values when accessing a cell. The Address Descramble circuit reverses the OpticRAM scramble. It transforms the Data from the Address Registers into a new address, which the OpticRAM decodes to access the desired pixel.

The circuit consists of 2 inverters, 3 Exclusive-OR's and a multiplexor (D2). The invertors and Exclusive-ORs provide the descramble function on the Row and Column addresses. The multiplexor selects between the descrambled Row and Column address' at the appropriate time and drives the address to the opticRAM. The multiplexor uses RASP to determine which address is selected. If RASP is high at the multiplexor SELECT input (D2-1), the B inputs, which are the descrambled Row Addressinputs, are selected. When RASP is low, the A inputs, or descrambled Column Address inputs, are selected. The descramble truth-table is available in the IS32 data sheet.


The purpose of the SOAK/ circuit is to prevent the refresh from reaching the OpticRAM. The OpticRAM is light sensitive only when it is not being refreshed. When INT is low (which is when the Refresh Register is active) and SOAK/ is low, the output of the NOR gate, B3-13, is high. This sets the multiplexor Enable input (D2-15) high and drives the multiplexor outputs low. I'he high NOR gate output at B3-13 also forces a low at the inverter output E3-8, which forces the outputs of the four AND gates (D4- 3,6,$,11) low. Thus, the OpticRAM address inputs remain low, and the refresh function is performed only on address 0, i.e., only Row 0 gets refreshed.

When SOAK/ goes high, the multiplexor and AND gate outputs are enabled and the refresh addresses reach the OpticRAM and the entire chip is refreshed, it insensitive to light. The SOAK/ command can be thought of as an electronic shutter control.

Din/Dout Circuit

This circuit controls the input to the OpticRAli Din (Data In) pin and also detects when a cell in the OpticRAM has been "exposed" to the low state. For a cell to be light sensitive, it must be initially charged to +5 volts. This is done by writing data into the cells. Due to the operation of the OpticPAM internal circuitry, a logic "1" must be written into all cells with row addresses between 0 and 127, and a logic "0" must be written into all cells with row addresses between 128 and 255. The most significant row address bit, Q7, is latched (during interrupt cycles) by flip-flop E4 on the falling edge of RASP. When the row address is between 0 and 127, row address bit Q7 is a 0, and when the row address is between 128 and 255, row address bit Q7 is a 1. The inverting output of flip-flop E4 (E4-8) is connected to the Data In pin on the IS32. Thus, the proper data will be presented to the OpticRAM to write each cell to +5 volts.

The Exclusive-OR gate (E2-8,9,10) compares the data out of the OPTICRAM with the data tht was read into it. Notice that the input to the Exclusive-OR gate at E2-8 is the complement of the value at the Din pin. Thus, if the OpticRAM cell being read out is still high, the two flip- flop outputs, E4-8 and E&-9, will be at opposite levels and the output of the Exclusive-OR (E4-10), will be high. Conversely, if the cell has been exposed to the low state, the two inputs to the Exclusive-OR will be the same and it's output, E4-10, will be low. The output of E4-10 propagates to the Transmitter circuit, where it is latched and transmitted to the computer.